Skip to main content

Code to Make the LED Blink

This is a very simple program, the desired target is to make the LED's on the BASYS2 board blink, and by blinking I mean a very visible turning on and off. This can be very easily achieved in verilog. The code can be found below:


module led_simple(
    input clock,
    input reset,
    output led, led2, led3, led4, led5
    );

reg [26:0] count; //A sizable 27 bit register so that the blink can be seen and is visible, too small a register will make the
      //register stay on as it will blink extremely fast.

always@ (posedge clock or posedge reset)
 begin
  if (reset)
   count <= 0;  //if reset button is pressed, initialize or reset the register
  else 
   count <= count + 1;  //otherwise increment the register
  end
  
assign led = count[26];   //MSB connected to output led. and the other outputes conncted as below
assign led2 = count[25];
assign led3 = count[24];
assign led4 = count[23];
assign led5 = count[22];
endmodule


The concept is very simple. I defined a 27 bit register to count from 27'b0 till 27'b1. Every time the MSB and the MSB-1, MSB-2... become 1 the LED connected to that bit will turn on, otherwise it will stay off.

The register can be of any size, but it should be large enough for it to take some time to activate the MSB thus making the blink nice and visible.

The above code has been tested and can be programed onto the BASYS2 board, using the BASYS2 .ucf file I posted. Ofcourse the file must be edited for it to work, only the required pins must be used. For example the original .ucf file for this code will be:


# Pin assignment for LEDs 
NET "led5" LOC = "n5" ; 
NET "led4" LOC = "p6" ; 
NET "led3" LOC = "p7" ; 
NET "led2" LOC = "m11" ; 
NET "led" LOC = "m5" ; 

# Pin assignment for pushbutton switches
NET "reset" LOC = "a7"; 

# Pin assignment for clock
NET "clock" LOC = "b8";
The above code can be seen working in the video here:

Comments

  1. Unknown30 October 2012 at 00:33

    these tutorials are great! I am a computer engineering student, and verilog is one of my subjects. Very helpful

    ReplyDelete
  2. Unknown7 March 2014 at 00:53

    Hi, I'm a computer science student and not familiar with engineering courses. I wanted to say thank you! Your articles just saved my life :-)

    ReplyDelete
  3. Unknown30 November 2016 at 15:38

    thank you to help us

    ReplyDelete
  4. provip3 September 2017 at 08:36

    Thank you very much. Extremely helpful and understandable

    ReplyDelete

Post a Comment

Popular posts from this blog

To Code a Stopwatch in Verilog

The stopwatch coded here will be able to keep time till 10 minutes. It will be a 4 digit stopwatch counting from 0:00:0 till 9:59:9. The right most digit will be incremented every 0.1 second, when it reaches 9 it will increment the middle two digits, which represent the second count. When it reaches 59 seconds it will increment the right most minute display. The stopwatch will be in the format M:SS:D. How to Create an Accurate Delay in Verilog: To make the stop watch an accurate device we need to be able to produce an accurate 0.1 second delay. I have already explained how to do this before in my decimal counter in verilog post. But since it is of great importance to the design will be explained in more detail here. Since we know that the BASYS2 (the one I am using, yours may be different) has a 50 MHz clock which means that the clock cycle is repeated 50M times in one second. So to create a 0.1 second delay we multiply the clock with the required time: 50MHz * 0.1 sec =
42 comments
Read more

Seven Segment LED Multiplexing Circuit in Verilog

The seven segment LED circuit uses seven different and individual LED's to display a hexadecimal symbol. It has 7 wires to control the individual LED's one wire to control the decimal point and one enable wire. The demo board I am using here consists of four such 7-segment LED's(As do any other demo board). To reduce the number of wires a multiplexing circuit is used to control the display. Using the multiplexing circuit the number of wires required to light up all 4 displays are reduced from 32 to 12 (8 data bits and 4 enable bits). All bits here are active low, such that to enable them a '0' is required. For example the figure below shows how to display a 3 on the seven segment. The multiplexing circuit can take 4 inputs and have only one output. But the inputs should be displayed on the output fast enough to fool the viewer into thinking all outputs are enabled individually and simultaneously. This is achieved by having an enable signal that changes so fast t
12 comments
Read more

Random Number Generator in Verilog | FPGA

In verilog a random number can be generated by using the $random keyword but that works only for simulation purposes and cannot be implemented. So when we need a random number for implementation i.e. in hardware it can be achieved using an LFSR (Liner Feedback Shift Register). An LFSR is simply a shift register with some of its bits (known as taps) XOR'd with themselves to create a feedback term. When implementing an LFSR it's width and it's repeatability must be kept under consideration .An N-bit LFSR will be able to generate (2**N) - 1 random bits before it starts repeating. For example a 30 bit LFSR will have 1073741823 random states before repeating, so for most practical purposes this can be considered true random. In an LFSR the MSB will always be the feedback point also the main thing to take care of while coding an LFSR is to know which bits are the taps (to be selected for XOR ). This is confusing as the taps are different for different size registers. For e
20 comments
Read more