Skip to main content

Binary Counter in Verilog | BASYS2

Now that we have the blinking LED in Verilog up and running, we can do an advanced version of the same project; a binary counter using the LED's.
Also this time I will be using the push button to increment the counter. So every time the push button is pressed the counter will be incremented by 1, the LED's will present the binary counter.

The code for the program is shown below:
module button_binary(
    input clock,
    input reset,
  input button,
    output led,
    output led2,
    output led3,
    output led4,
    output led5,
    output led6,
    output led7,
    output led8
    );

reg [7:0]count;

always @ (posedge button or posedge reset)
 begin
  if (reset)
   count <= 0;
  else if (button)
   count <= count + 1;
 end
 
assign led = count[0];
assign led2 = count[1];
assign led3 = count[2];
assign led4 = count[3];
assign led5 = count[4];
assign led6 = count[5];
assign led7 = count[6];
assign led8 = count[7];


endmodule

The above program is so simple it needs no commenting, the thing to note here though is the always block. In place of the usual clock I used the push button (always @ posedge button). This is not the best method, but if I use clock here without any debouncing mechanism the counter will not be accurate, i.e. every time the push button is pressed due to the bouncing problem related to push buttons the counter will be incremented many times for each time it is pressed.

I will design the de-bouncing circuit in a later post.

The .ucf file for the above design for the basys2 board is shown below:

# Pin assignment for LEDs
NET "led8" LOC = "g1" ; 
NET "led7" LOC = "p4" ; 
NET "led6" LOC = "n4" ; 
NET "led5" LOC = "n5" ; 
NET "led4" LOC = "p6" ; 
NET "led3" LOC = "p7" ; 
NET "led2" LOC = "m11" ; 
NET "led" LOC = "m5" ; 

# Pin assignment for pushbutton switches
NET "reset" LOC = "a7"; 
NET "button" LOC = "m4"; 

# Pin assignment for clock
NET "clock" LOC = "b8";

The working of the above code is shown below:

Comments

  1. Unknown27 May 2015 at 07:39

    Dear Faraz,
    I have been trying your code in a DE 2 115 altera board, no error shows in the code but nothing happens when in the board . (I have done the pin configuration correctly)

    ReplyDelete
  2. Faraz Khan27 May 2015 at 14:03

    Khandaker, if the code shows no error then then the only thing left is something went wrong in the implementation. I recommend you read up on the proper implementation procedure of the IDE you are using and also to verify again if the .ucf file is accurate.

    Also when you say no error, does that also mean that the simulation is working as it should?

    ReplyDelete

Post a Comment

Popular posts from this blog

To Code a Stopwatch in Verilog

The stopwatch coded here will be able to keep time till 10 minutes. It will be a 4 digit stopwatch counting from 0:00:0 till 9:59:9. The right most digit will be incremented every 0.1 second, when it reaches 9 it will increment the middle two digits, which represent the second count. When it reaches 59 seconds it will increment the right most minute display. The stopwatch will be in the format M:SS:D. How to Create an Accurate Delay in Verilog: To make the stop watch an accurate device we need to be able to produce an accurate 0.1 second delay. I have already explained how to do this before in my decimal counter in verilog post. But since it is of great importance to the design will be explained in more detail here. Since we know that the BASYS2 (the one I am using, yours may be different) has a 50 MHz clock which means that the clock cycle is repeated 50M times in one second. So to create a 0.1 second delay we multiply the clock with the required time: 50MHz * 0.1 sec = ...
42 comments
Read more

Seven Segment LED Multiplexing Circuit in Verilog

The seven segment LED circuit uses seven different and individual LED's to display a hexadecimal symbol. It has 7 wires to control the individual LED's one wire to control the decimal point and one enable wire. The demo board I am using here consists of four such 7-segment LED's(As do any other demo board). To reduce the number of wires a multiplexing circuit is used to control the display. Using the multiplexing circuit the number of wires required to light up all 4 displays are reduced from 32 to 12 (8 data bits and 4 enable bits). All bits here are active low, such that to enable them a '0' is required. For example the figure below shows how to display a 3 on the seven segment. The multiplexing circuit can take 4 inputs and have only one output. But the inputs should be displayed on the output fast enough to fool the viewer into thinking all outputs are enabled individually and simultaneously. This is achieved by having an enable signal that changes so fast t...
12 comments
Read more

Random Number Generator in Verilog | FPGA

In verilog a random number can be generated by using the $random keyword but that works only for simulation purposes and cannot be implemented. So when we need a random number for implementation i.e. in hardware it can be achieved using an LFSR (Liner Feedback Shift Register). An LFSR is simply a shift register with some of its bits (known as taps) XOR'd with themselves to create a feedback term. When implementing an LFSR it's width and it's repeatability must be kept under consideration .An N-bit LFSR will be able to generate (2**N) - 1 random bits before it starts repeating. For example a 30 bit LFSR will have 1073741823 random states before repeating, so for most practical purposes this can be considered true random. In an LFSR the MSB will always be the feedback point also the main thing to take care of while coding an LFSR is to know which bits are the taps (to be selected for XOR ). This is confusing as the taps are different for different size registers. For e...
20 comments
Read more