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Serial Receiver and Transmitter (UART) in Verilog | FPGA

Note: This was a post I wrote back in 2014 as I was teaching myself Verilog, but never got around to finishing the code for it and thus this post remained as a draft. I apologize that this is not in line with my other previous blog posts as it does not have a working code and is not demonstrated working in a video. But I am publishing this in hopes that someone researching this topic may find my introductory text on the topic useful. UART stands for Universal Asynchronous Receiver and Transmitter. It is a system that is a capable of sending parallel data using a serial line. As the name indicates, the UART consists of a transmitter and a receiver. The transmitter accepts data in parallel and then by using a shift register send the data out bit by bit using predetermined parameters. Similarly the receiver accepts the data serially and then compiles the data using a shift register. Data is recognized by following a fixed format while transmitting and receiving, data sent consists of a s