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Serial Receiver and Transmitter (UART) in Verilog | FPGA

Note: This was a post I wrote back in 2014 as I was teaching myself Verilog, but never got around to finishing the code for it and thus this post remained as a draft. I apologize that this is not in line with my other previous blog posts as it does not have a working code and is not demonstrated working in a video. But I am publishing this in hopes that someone researching this topic may find my introductory text on the topic useful.


UART stands for Universal Asynchronous Receiver and Transmitter. It is a system that is a capable of sending parallel data using a serial line. As the name indicates, the UART consists of a transmitter and a receiver. The transmitter accepts data in parallel and then by using a shift register send the data out bit by bit using predetermined parameters. Similarly the receiver accepts the data serially and then compiles the data using a shift register. Data is recognized by following a fixed format while transmitting and receiving, data sent consists of a start bit, data bits an optional parity bit and finally a stop bit. The transmission line will stay at 1 when it is idle, transmission starts when a 0 (start bit) is detected. This is followed by 8 data bits, followed by an optional parity bit. The parity bit is used for error detection, it can either be even parity or odd parity. The optional parity bit is followed by the stop bit(s) which marks the end of transmission for that word. The number of stop bits can be 1, 1.5 or 2.

The 'set parameters' that I mentioned earlier are important because no clock information is sent over the transmission line and smooth operations are ensured by these parameters, which are the baud rate (bits per second), the number of data bits (some systems use 6 or 7 data bits instead of the standard 8) and the number of stop bits. The commonly used baud rates are 2400, 4800, 9600 and 19,200.


 For example the above image shows data transfer that starts with the start bit, followed by 8 data bits, the optional parity bit and finally stop bit. Do note that the least significant bit (LSB) is always sent first.

As mentioned before no clock information is sent during data transmission and the receiver is still able to detect every bit. It achieves this by using an oversampling procedure. Oversampling procedure is to sample every incoming bits multiple times. For 1 stop bit the most common oversampling rate is 16, which means that each incoming bit is sampled 16 times. For 1.5 stop bits the over sampling rate will be 24 and for 2 stop bits the oversampling rate will be 36.  Understanding the oversampling procedure is essential to grasping the concept of serial communication.

Oversampling Procedure in Serial Communication


Since I will be using 1 stop bit the oversampling rate will be 16. I am going to use a couple counters to keep track of the sampling process. Now assume that the parameters we are using consists of 'x' data bits. The oversampling will proceed as follows:
  • As soon as the start bit is detected at the receiver, the sampling counter will start and count till 7 (half of 16). This ensures that the middle of the start bit is reached.
  • Now using another counter start counting till 15 (starting from 0, this makes it 16 counts). When 15 is reached we can be sure that the receiver has reached the middle of the first data bit. Move this bit to a shift register and restart this counter. Repeat this step until all data bits are accepted or repeat it 'x - 1' times.
  • Use the same counter procedure to accept the optional parity bit and the stop bit.
Because of this oversampling procedure the baud rate will be very low as compared to the clock rate. And that is why this method is not recommended for high data rate transmission.

Designing the Baud Rate Generator


The next step is to design the baud rate generator. As mentioned above the commonly used baud rates are 2400, 4800, 9600 and 19,200. Here I will be using the 19,200 baud rate. To design a counter for our designated baud rate is connected to the selected oversampling rate and since our over sampling rate is 16 ( 16 times the baud rate) we have 19,200 * 16 = 307,200. Now since I know the board I am using (BASYS2) has a 50 MHz clock, I can calculate the counter length needed for this by:

50M / 307,200 = 162.7 ~~ 163.

The width of the register that will count to 163 can be calculated by using the method explain here: To calculate an accurate time delay in verilog. So by using the log method I know that I need an 8 bit wide register to count up to 163.

Based on the nature of this design I will be using Finite State Machine with Data path (FSMD) to code this receiver. The finite states will follow the same procedure as explained above.

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