Learn Verilog by Example

This one is going to be a quick easy project. The objective here is to get use the 7-segment LED display on the board to display a scrolling text. it should be slow enough so that it can be easily read. I have made the delay between each word shift to be 1 second. This is long enough to read the text comfortably without missing anything. I have explained in my previous post how to create an accurate delay using verilog, you can read about it there: Create accurate delay in Verilog . Now since I need a 1 second delay here the counter monitoring this count must count to 50,000,000. And the register needed to hold this count must be 29 bits wide. Using this method you can scroll and display anything. Here I have chosen to display the text "Hello There" to scroll across the LED's and appear to be continuous without any stops. The concept is pretty simple. I create a separate counter that increments every time a count of 50,000,000 is reached. This counter will count till

A FIFO(First in First Out) buffer is an elastic storage usually used between two subsystems. As the name indicates the memory that is first written into the FIFO is the first to be read or processed. A FIFO has two control signals i.e. write and read. When write is enabled data is written into the buffer and when read is enabled data is "removed" from the buffer to make room for more data. This concept of write and read (remove) can be best understood from the conceptual diagram of a FIFO below: As can be seen, once the data is read, it can be considered as removed and thus allowing more data to be written into the buffer. Implementation of FIFO in Verilog To implement FIFO in verilog imagine the memory components to be arranged in a circular queue fashion with two pointers; write and read . The write pointer points to the start of the circle whereas the read pointer points to the end of the circle. Both these pointers increment themselves by one after each read or wr

The stopwatch coded here will be able to keep time till 10 minutes. It will be a 4 digit stopwatch counting from 0:00:0 till 9:59:9. The right most digit will be incremented every 0.1 second, when it reaches 9 it will increment the middle two digits, which represent the second count. When it reaches 59 seconds it will increment the right most minute display. The stopwatch will be in the format M:SS:D. How to Create an Accurate Delay in Verilog: To make the stop watch an accurate device we need to be able to produce an accurate 0.1 second delay. I have already explained how to do this before in my decimal counter in verilog post. But since it is of great importance to the design will be explained in more detail here. Since we know that the BASYS2 (the one I am using, yours may be different) has a 50 MHz clock which means that the clock cycle is repeated 50M times in one second. So to create a 0.1 second delay we multiply the clock with the required time: 50MHz * 0.1 sec =

Since I have already made a detailed post regarding 7 segment LED multiplexing , this post is going to be a short one, in which I will only explain the code via comments in code. Here I am going to make a 2 digit counter that counts from 00 to 99 and then rolls over back to 00. The counter will increment every 0.1 second. The 0.1 second interval is produced by another counter that will produce an enable tick every 0.1 second to increment our main counter. How to make a 0.1 second accurate delay in Verilog We know that the board being used has a 50 MHz clock. So to produce a 0.1 second delay simply multiply the two.. 50Mhz * 0.1 sec = 5000000. So every 5M ticks is equal to 0.1 second. So using the simple log formula ( (x)log(2) = log(5000000) ) we can calculate that a 23 bit wide register will be able to hold a count of 5000000. The code for this counter is given below: module twodigit_onefile( input clock, input reset, output a, output b, output c, outp

The seven segment LED circuit uses seven different and individual LED's to display a hexadecimal symbol. It has 7 wires to control the individual LED's one wire to control the decimal point and one enable wire. The demo board I am using here consists of four such 7-segment LED's(As do any other demo board). To reduce the number of wires a multiplexing circuit is used to control the display. Using the multiplexing circuit the number of wires required to light up all 4 displays are reduced from 32 to 12 (8 data bits and 4 enable bits). All bits here are active low, such that to enable them a '0' is required. For example the figure below shows how to display a 3 on the seven segment. The multiplexing circuit can take 4 inputs and have only one output. But the inputs should be displayed on the output fast enough to fool the viewer into thinking all outputs are enabled individually and simultaneously. This is achieved by having an enable signal that changes so fast t

So you have made a counter and after programming it onto your board you realize that every button press increments the counter by 30 or 40 units. This problem is knows as bouncing and to overcome this a debouncing circuit is needed to compensate for the mechanical button bounces. The push buttons and switches on the FPGA boards are mechanical devices and tend to bounce multiple times when pressed. And since the code related to the button is usually placed in the always @ (posedge clock) block, every bounce of the button is picked up and processed. It has been found that the bounces last around 20 ms after which it stabilizes. The debouner circuit should be able to filter out these bounces and only pick up the stabilized state of the button. Since it is known that the bounces last around 20 ms the first thing the code should have is a timer, a timer that will outlast the 20 ms of instability. I will use a 10 ms counter and after every 10 ms will check the state of the button, if it

I did not initially plan on adding such topics to this blog but the reason I'm covering this is because I had a great deal of difficulty coding a FIFO buffer as I also was not clear regarding this concept. I was writing writing combinational logic in sequential blocks, which I read is not a good idea. In an always block expressions and variables can be connected using either a blocking or non-blocking statement. Knowing when to use which will make the code work. As a general rule blocking assignments are used to describe combinational logic and non-blocking are used to describe sequential logic. Blocking Assignment: Simply put this follows more of a C and C++ style, that is the lines of code are processed one after an other. The syntax for this blocking assignment is: (variable) = (expression); So when this line is executed the expression on the right hand side is calculated and the value is assigned to the variable on the left hand side. While this expression is b

Now that we have the blinking LED in Verilog up and running, we can do an advanced version of the same project; a binary counter using the LED's. Also this time I will be using the push button to increment the counter. So every time the push button is pressed the counter will be incremented by 1, the LED's will present the binary counter. The code for the program is shown below: module button_binary( input clock, input reset, input button, output led, output led2, output led3, output led4, output led5, output led6, output led7, output led8 ); reg [7:0]count; always @ (posedge button or posedge reset) begin if (reset) count <= 0; else if (button) count <= count + 1; end assign led = count[0]; assign led2 = count[1]; assign led3 = count[2]; assign led4 = count[3]; assign led5 = count[4]; assign led6 = count[5]; assign led7 = count[6]; assign led8 = count[7]; endmodule The above program is so simple it ne

This is a very simple program, the desired target is to make the LED's on the BASYS2 board blink, and by blinking I mean a very visible turning on and off. This can be very easily achieved in verilog. The code can be found below: module led_simple( input clock, input reset, output led, led2, led3, led4, led5 ); reg [26:0] count; //A sizable 27 bit register so that the blink can be seen and is visible, too small a register will make the //register stay on as it will blink extremely fast. always@ (posedge clock or posedge reset) begin if (reset) count <= 0; //if reset button is pressed, initialize or reset the register else count <= count + 1; //otherwise increment the register end assign led = count[26]; //MSB connected to output led. and the other outputes conncted as below assign led2 = count[25]; assign led3 = count[24]; assign led4 = count[23]; assign led5 = count[22]; endmodule The concept is very simple. I defined a 27 b

Here is the user constraint file (.ucf) file that shows every pin location on the board. This file will be used in every project here as without it programming the FPGA is impossible. # Pin assignment for LEDs NET "ld<7>" LOC = "g1" ; NET "ld<6>" LOC = "p4" ; NET "ld<5>" LOC = "n4" ; NET "ld<4>" LOC = "n5" ; NET "ld<3>" LOC = "p6" ; NET "ld<2>" LOC = "p7" ; NET "ld<1>" LOC = "m11" ; NET "ld<0>" LOC = "m5" ; # Pin assignment for slide switches NET "sw<7>" LOC = "n3"; NET "sw<6>" LOC = "e2"; NET "sw<5>" LOC = "f3"; NET "sw<4>" LOC = "g3"; NET "sw<3>" LOC = "b4"; NET "sw<2>" LOC = "k3"; NET "sw<1>&qu