Learn Verilog by Example

This post will be about programming a reaction timer in verilog and make it ready for FPGA implementation which in our case will be on the BASYS2 (Spartan 3E) board but can be programmed for any other board by simply changing the .ucf file. The reaction timer or reflex tester will check and time how fast you can respond after seeing a visual stimulus or in other words it will test your hand eye co-ordination. The code for this is a bit more busy than any of my other projects, but it has been heavily commented so just by reading the code you can easily understand what is going on. The code will be followed by a video demonstration in Isim along with it working on the FPGA board. Here we will be using three inputs; reset , start , stop and one output led along with displaying the time on the seven segment display . When the reset button is pressed it will obviously reset all registers and counters and will make the system ready for the next reflex test. Also when in this state it